The subject application is related to subject matter disclosed in Japanese Patent Application No. H 11-317887 filed on Nov. 9, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
The present invention relates to a semiconductor device having memory circuits.
Memory-logic LSIs (system LSIs) have been popular recently. These LSIs are used to constitute a specific system by mounting memory circuits and logic circuits on one chip. Circuits that are usually mounted on separate chips are mounted on one chip for memory-logic LSIs, thus requiring higher performance, lower power consumption and miniaturization (reduction of components).
There are two types for memory-logic LSIs. One is a custom LSI having custom logic and memory circuits. The other type is a ASIC (Application Specific IC) that is a semi-custom LSI having memory circuits memory macro cells) designed as function blocks.
ASICs are very popular for their flexibility to a variety of users"" demands because they can be rearranged in a short turn around time.
As memory macro cells for ASICs, re-configurable memory macro cells have been developed.
Re-configurable memory macro cells are, however, disadvantageous in high cost for testing each macro cell due to different test programs for a plurality of different types of products using memory macro cells configured differently.
Moreover, memory macro cells cannot be tested at the same time due to different address spaces for a plurality of memory macro cells mounted on a one-chip memory-logic LSI.
A purpose of the present invention is to provide a LSI having re-configurable memory circuits with a low cost for memory testing and also switching in performance specifications.
The present invention provides a semiconductor device including: at least one logic circuit; and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells, wherein addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal.
Moreover, the present invention provides a semiconductor device including: at least one logic circuit; and a plurality of memory macro cells having a plurality of memory cell array blocks each composed of a plurality of memory cells, wherein at least one of the memory macro cells is switched in configuration as having the same length of rows or columns between the memory cell array blocks in test, the configuration being different from a configuration of row and column for a regular operation.
Furthermore, the present invention provides a semiconductor device having a plurality of memory macro cells, each memory macro cell including: a plurality of memory cell array blocks each having a plurality of memory cells, composed of rows and columns; a decoder configured to decode a row or a column address signal to select at least one memory cell located on a row or a column corresponding to the decoded address signal; and a switching circuit configured to convert the row or the column address signal in response to a switching signal and supply the converted signal to the decoder to set address spaces having the same number of rows or columns between the plurality of memory cells.
Moreover, the present invention provides a method of testing a semiconductor device having at least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells, including the step of selecting addresses for designating the memory cell array blocks among external addresses by a switching signal.
Furthermore, the present invention provides a method of testing a semiconductor device having at least one logic circuit and a plurality of memory macro cells having a plurality of memory cell array blocks each composed of a plurality of memory cells, including the step of switching at least one of the memory macro cells in configuration as having the same length of rows or columns between the memory macro cells, the configuration being different from a configuration of row and column for a regular operation.